I'm quite new with AD9361 FSCOMM2 and I need to use the fastlock mode to accelerate my frequency shift.
When I shift in a previously stored profile (ad9361_fastlock_store() ) with ad9361_fastlock_recall() , the pll convergence is done in approximately 100 us after ad9361_fastlock_recall() calling, instead of 500 us with a classical rf_pll_set_rate calling, so that's a good point.
The thing is that when I use ad9361_fastlock_recall(), I also must execute the all rf_pll_set_rate() sequence to make it works, and I don't understand why.
I thought in a first time that ad9361_fastlock_recall() achieves the all PLL reconfiguration as my profile exists in fastlock registers and I don't understand why I need to also call the normal sequence (rf_pll_set_rate ).
Could someone explain me the issue ?