Can you help support the Delta-sigma NF and reference buffer NF of HMC704?
I can't found that in the datasheet of HMC704.
By 'NF' I assume you mean noise figure. We do not have a noise figure parameter for the reference circuit. What matters is the composite noise performance of the entire PLL device. This can be effectively modeled using ADI's SimPLL tool which is available at --> https://form.analog.com/Form_Pages/RFComms/ADISimPll.aspx
This tool will also show the noise effect of the Delta-Sigma Modulator.
Thanks for your help.When simulate HMC704, reference buffer noise contributions as below 0dB,no contribution at all?
About Delta-sigma noise contributions,only mode select and so on.In fact, it will affect the noise distal descent speed.
In the PLL Design tool all noise contributions from the PLL are lumped into the 'Phase Detector Noise' specification so the 'Reference Path Noise' and 'RF Divider Noise' are effectively zero'ed. We do not have individual noise parameters for these three circuit blocks. The HMC PLL's have two operating modes, A & B, both 3rd Order DSM's. Changing between these two modes will show a difference in the distribution of the noise.
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