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configuration line rate

Question asked by Bouchaib on Aug 15, 2016
Latest reply on Mar 22, 2018 by yzzhsx123

Hi Istvan,

 

Thanks for your reply .

I have a question about the procedure to change the rate .

I need to modify the parameter configuration in the file axi_jesd_gt  IP or in the block design level: hdl <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2>/projects <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects>/daq2 <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects/daq2>/kcu105 <https://github.com/analogdevicesinc/hdl/tree/hdl_2015_r2/projects/daq2/kcu105>/system_bd.tcl.

 

     source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl

source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl

 

p_sys_dmafifo  axi_ad9680_fifo 128 16

p_sys_dacfifo  axi_ad9144_fifo 128 10

 

source ../common/daq2_bd.tcl

 

set_property -dict  $axi_daq2_gt

set_property -dict  $axi_daq2_gt

set_property -dict  $axi_daq2_gt

 

At the beginning i think the parameter are overwrited with  system_bd.tcl because the project is created for the first time.

But when i re-launch a new generation bitstream with Vivado GUI, the file  system_bd.tcl is considered or not if i modified it (

set_property -dict  $axi_daq2_gt)?

 

 

Thanks for your help,

 

Bouchaib

 

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