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AD9954 synchronization problem

Question asked by IgorVladim on Aug 13, 2016
Latest reply on Sep 26, 2016 by JLKeip

Hi.

I need to build test signal generator which produce three 27-30Mhz sinusoidal output signals with programmable phases. For this purpose I use 3 AD9954 connected as following.
Structure.png

 

All this stuff is situated at single PCB. Initially I took as a reference point the concept where single 25MHz crystal oscillator connected to Master DDS produces clock to other slaves via CRYSTAL_OUT pin of this chip. There were signal strenght issues with CRYSTAL_OUT pin which i fixed with simple 74LVC1G17 buffer. But after final assembling and programming I understood that it was wrong solution - syncronization did not work at all. For now I made some kind of workaround on this PCB and now it looks like as on picture. I measured perfomance of this PCB "clocking tree" - please read text under picture.

I understand that it is not good way to connect LVDS oscillator as shown but I want to evaluate my current PCB in this way. For now it distributes clock to all three DDS chips via independent differential pairs, their length is equal and approximately 2.5cm each. All 3 DDS chips get their reference frequency and able to provide stable frequency output.

IO_UPDATE signal is buffered at PCB connector and delivered to DDS chips inputs with equal length traces.

 

This PCB is connected to MCU which issues RESET signal to all DDS chips, writes configuration, Frequency Tuning Words and makes IO_UPDATE. Chips configured for Automatic Clearing of Phase Accumulator at IO_UPDATE, slaves configured with Automatic Sync Enable bit set. Then MCU writes Phase Offset Words and makes IO_UPDATE again.

After this routine DDS chips work untill next RESET and configuration cycle.

 

Mostly it initializes well - phase offsets of all three outputs are very small and barely visible at oscilloscope (not exactly matched but I understand that it is due to my workaround with not closely matched differential transmission lines for REF_CLK signals).

BUT in some cases one of DDS chip outputs may be shifted in phase for a constand delay referenced to master output. For some reason I could see only 4ns, 12ns and 16ns which is multiple of 4ns SYS_CLK period - but never 8ns ). I can't understand why there is no stable synchronization? Propagation delays of SYNC_CLK are lower then SYS_CLK period 4ns. Also if I tried to turn off Automatic Sync Enable or even turn off SYNC_CLK from master for comparison (physically SYNC_CLK signal is absent) - behaviour is similar. It looks like there is no synchronization at all.

 

I also tried to distribute LVDS 250MHz clock serially beginning from Master DDS and ending at 2-nd Slave DDS with single transmission line and 100R termination which is more proper way. Output signals were more phase shifted up to 1ns due to more transmission line length imbalance but there was also same problem with no stable synchronization.

 

So my questions:

1) Looks like there should be higher phase noise in my case but synchronisation should be stable? Or may be I am wrong? Why there may be 16ns delay which is 4 SYS_CLK periods if there is 1ns propagation delay of SYNC_CLK? 

2) May be my synchronization routine is wrong? Must I do something else (not only setting Automatic Sync Enable in Slave DDS chips). Note that I wait 10ms after config IO_UPDATE and before writing phase offsets. I also tried Software manual Synchronization and I could manually do this 4ns shift at one channel when this command was not issued to all chips.

3) Is it correct that when there is 1ns propagation delay from Master SYNC_CLOCK to Slaves SYNC_IN - then I do not need additional SYNC_CLK buffering? Will there be enough only single LVDS clock distributor/splitter chip from LVDS oscillator for my purposes? Can you suggest such chip - may be not complicated "clock-cleaner" with onboard PLL and SPI interface but simple clock distributor?

 

Thanks in advance )))

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