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AD-FMCDAQ2-EBZ. AD9680 - "no input clock detected"

Question asked by willsor on Aug 15, 2016
Latest reply on Nov 16, 2016 by willsor

I am trying to build a design for the AD9680 using the default link parameters and a Xilinx JESD IP core.

My SPI interface is working, but I don't seem to get any meaningful output from the JESD lanes.


Reading AD9680 register 0x11C, I read a value of 0x00, meaning "no input clock detected"

I've been trying to jump start the AD9523 but I don't know how.


I have tried writing AD9523 address 0x233 with 0x00 ( the power down control).

I have tried writing AD9523 address 0x193, the power-down channel bit, with a 0.


However the AD9523 address 0x230 "status monitor" gives me a value 0x00 (GND).

My gtN_rx_rxdata[31:0] channels are giving out a pattern of 0x4a4a4a4a or 0xb5b5b5b5



What is the startup procedure for this clock chip? What SPI commands do I need to run?