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HMC6981LS6 power off

Question asked by VTesi on Aug 12, 2016
Latest reply on Sep 19, 2016 by SMcBride

Hi SMcBride,

Here I follow an old  discussion (I was not able to reopen https://ez.analog.com/thread/80040 ).

In our design we followed a dual approach, that is: a slow action on gate voltage to put HMC6981LS6 OFF in order to conserve power and reduce power dissipation in our device (it's tiny) and a fast action switching the input power to HMC6981LS6 on/off.

In slow action HMC6981LS6 gate voltage is switched through a bias network between two values: about  -1V (ON) and about -2.5V (OFF).

Unfortunately we observe a degradation in some HMC6981LS6 devices: the gate, which is normally high impedance at DC, becomes low impedance and the device looses much dBs of gain, becoming useless.

The input power is about +10 dBm.

My question is:

if the gate is polarized at -2.5V (in order to put the device in low power) and during test the input power is switched ON, is it possible to have gate junction breakdown ? That is, breakdown can happen if the instantaneous voltage ( DC +  RF) go beyond device ratings ?

If so,  the approach of changing gate voltage to power off the device, discussed in the old thread reported, poses serious hazard lowering the margin for gate breakdown.

Thanks, Vasco

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