We are simulating ibis of AD9517 in Hyperlynx at 200MHz. We are getting warning as in the attachment. At this low frequency, clock isn't looking good as it isn't flat on the levels. Please suggest how can I improve this.
It's very difficult to see your schematic clearly, but it appears that you don't have a 100 ohm termination resistor at the destination. If not, you'll need to add one. If that doesn't fix it, I'd check to see if you get the same waveform without the vias in the middle of the transmission line.
Internal 100ohm termination of the FPGA is used in the model.
Also to bring to your notice, there are two cautions with respect to the model as shown in the attached image.
What happens if you remove the vias?
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