I have come across a board with multiple AD9915 that shall be synchronized from one master DDS through SYNC_OUT distributed to slaves' SYNC_IN via an AD9520. REF_CLK is running at 2.4GHz.
From reading other posts and app notes, it seems to be important that internal SYNC_IN and REF_CLK are properly aligned so that SYNC_IN transitions within a period of REF_CLK.
* Is the most important thing that the SYNC_IN transition occurrs during the REF_CLK transition from low to high or are there other constraints?
* If the SYNC_IN signal path is poorly designed, the slope of the SYNC_IN may be slow - in that case it is important to know the window within where SYNC_IN actually transitions - can this be found?
* I notice from the datasheet that rise time of (20%-80%) of SYNC_OUT is 1350ps - quite a bit longer than one period of REF_CLK. How is this handled?
At the moment, I'm trying to get a better understanding of the system and would like to know what could happen if the alignment drifts.
* Assuming that a proper synchronization is _not_ performed, but all DDSs are otherwise properly programmed, can it be that output signal (programmed to fixed frequency, no modulation) will be unstable in frequency or will there only be an unknown phase difference between the different DDSs?
* Is there any way of telling that the DDS has received properly aligned SYNC_IN and REF_CLK? Understanding that skewing may change with temperature, it would be valuable to be able to read out some kind of status signal when the signals are properly aligned. It would then be possible to run an automatic calibration for the synchronization.
Any comments would be highly appreciated!