pll settings are mode0=0 mode1=1 fs=96khz. yet the adau puts out 192khz when the frame sync is set at internalclck /512.. does the dsp run at 100Mhz ? the loop filter avg voltage is 3.3V, maxed out.
correction the loopfilter is at 1.3V
OK , found it
caugth again by the incorrect PLL chapter on page 18.
here it reads Mclk=256 fs then mode0=0 mode1=1 or said differently Mclk=24.576 fs=96khz.
the true story is just the divide factor of the pll to get to a 50MIPS clock. and that should be 2 for a 24.576 clk or both modes=1 .. how did AD mess up the datasheet so much ...
anyway I found out this way that the 1701 was running at 100MIPS as it did put out 192khz when the HW register was set as masterclock/512. overclockers are welcome ! not all chips run at 100MIPS it seems..
Yes, the data sheet is confusing. Thus you are not the first to inadvertantly overclock a -1701, and in the other case I'm aware of, the thing also ran fine. Perhaps not for long, however...
I immediately checked the temperature when I found out it was overclocked. not much temp rise, but I had the ADC's turned off, that saves power/heat
Retrieving data ...