I am using a AD9523-1 and I am getting some jittering on the PLL1 output.
I have an AD9548 feeding 80Mhz to AD9523-1 which in feeds 10MHz to a number of other AD9523-1s. All the AD9523-1 seem to have this jitter. I can make the issue worse by touching with either with my finger or DSO probe onto pin 7 (LF1_EXT_CAP).
I have 80MHz LVPECL into REFA, a CVHD-950-80MHz on OSC_IN_N and OUT0 connected to ZD_IN. All outputs are 10MHz LVDS. Attached are the register values.
With my DSO on 2.000ns I see the 10Mhz output with jitter, its moving back and forth about 0.5ns at a rate of about 2.5Hz, relative to the REF A 80Mhz input.
All the status registers for the PLLs and References say they are locked and OK.
I ran ADISim for the AD9523-1 and it suggests I use a 15nF for FL1_EXT_CAP. I had 0.33uF in there initially (from the FMCOMMS1 schematic). The cap seems to make very little difference to the jitter. What makes a big difference is setting Rzero to 883k and PLL1 to full scale 63.5uA. This gets me to the 0.5ns jitter. If reduce the current from full scale or reduce Rzero, the jitter gets much worse.
How do I reduce the 0.5ns jitter in PPL1 of the Ad9523-1, it should be about 350fs?