It would appear from the datasheet that IEXC0, IEXC1, and GND_SW could be used as digital outputs (when they are not needed and/or used for their direct purpose).
In case of IEXC0 and IEXC1, suitable pull-down resistors would set these outputs "Low", and activating one or both of IEXC0 and IEXC1 would set these outputs "High". It is understood that the control would be "slow", and it will only be usable with a high-input-impedance load, such as an input of a CMOS gate.
Likewise for the GND_SW pin, only with a pull-up resistor.
Looks like the "digital" signal swing of these "pseudo-outputs" will be full supply voltage for GND_SW, and perhaps AGND to [AVDD - 0.7V] for IEXCx pins.
1.) What is the leakage spec for the IEXC0, IEXC1, and GND_SW -- when these functions are OFF? Is it similar to the Analog inputs, in the tens of nanoAmps, or similar to digital I/O (+/-1 uA at room, +/-10 uA at elevated temperature)?
2.) While IEXC0 and IEXC1 have defined compliance range of [AGND − 30 mV] to [AVDD - 0.7V] ---- what is the allowed range for the GND_SW pin? Can it be pulled-up to 3.3 V like the rest of the digital pins? Or -- should the voltage on GND_SW be restricted to between AGND to AVDD?