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Why is HPC required for multilane JESD204B?

Question asked by htorke on Aug 4, 2016
Latest reply on Aug 4, 2016 by TonyM

Can someone explain the connector requirement for JESD204B?


On the AD9371 evaluation board, an HPC FMC connector is used. HPC is not widely used among processor baseboards due to the high pin count and IO utilization, so if there was a way to use the LPC, that would be more convenient. I notice that there are more than enough unused pins on the LPC compatible lanes to fit the additional 6 JESD lanes, and yet for some reason all but 2 lanes are allocated to the HPC only rows. Is there a specific reason these pins need to be used and the other pins on the FMC connector cannot be used?