I am having trouble understanding the clock signals used in the DDS section and the ramp generation section of AD9914. Figure 30 of the data sheet shows "DDS_CLK" going into the DDS accumulator. The equations for "FTW" and "fout" imply that the frequency of DDS_CLK is "fSYSCLK", and my device behaves this way (I use 3.2 GHZ). But in the digital ramp section on page 24 it says that the DDS clock runs at 1/24 of fSYSCLK. Do the clocks in Figure 37 and Figure 30 have different rates?