I have a question AD9200.
AD9200 has Data Valid Delay 25ns on Figure31. Timing Diagram.
But I want to know Setup/hold time.
If you know please teach me ..
Thank you for your question.
The timing diagram in AD9200 Figure 31 shows output data delay from the clock. I believe that the terms "setup-time" and "hold-time" are properties and requirements of the receiver inputs (often an FPGA). I believe those requirements will be determined by the receiver design and not the ADC outputs. Of course, the receiver design and timing requirements will need to be compatible with the output timing of the ADC.
Please let me know if you would like to discuss further.
Thank you for your answer.
I see your answer.
Retrieving data ...