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XXXXXXXXXX Output Clock Level Compatability

Question asked by SureshSurya on Aug 3, 2016
Latest reply on Aug 10, 2016 by JLKeip

Hi,

 

I am using XXXXXXXXXX for buffering 100 MHz Differential Ended clock. Vodiff = 250 to 450 mV, Vocm = 1100 to 1375 mV. I am using AD9643 ADC to which the output of the XXXXXXXXXX is connected. The input level of AD9643 are Vidff = 300 to 3600 mV, Vicm = 900 to 1400 mV. The Vodiff and Vidiff levels are not compatible. Can this be adjusted by varying the termination resistor?

 

I also require power dissipated in XXXXXXXXXX when the device is input clock is 100 MHz.

 

Thanks in advance.

 

Regards

Surya

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