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ADSP-BF70x Deep Sleep current reduction via L2CTL_PCTL

Question asked by pinaz on Aug 2, 2016
Latest reply on Aug 4, 2016 by pinaz

Analog's tech support gave me the brush off ("we think you are getting confused"), but I'm hoping that I might reach the author (JoeT?) of "ADSP-BF70x Guide to Power Estimation" via this forum.


I'm noticing two mechanisms that influence ADSP-BF707 power consumption in Deep Sleep (Analog tech support calls it "DPM Deep Sleep"), but are not mentioned as doing so in any Analog Devices documentation that I can find.


One mechanism is the L2CTL_PCTL register.  There is a BK8SD bit that turns off the mask ROM, and then additional bits to shut off 1/8th fractions of the L2 SRAM.


Per the attached graph (results obtained via a BF707-EZKIT with engineering sample silicon), I'm seeing non-trivial power savings by exercising these bits.


That exercising BK8SD alone seems to remove roughly 0.120 to 0.130 mA from the current consumption of VCORE seems quite relevant.  Exercising the shutdown bits for the L2 SRAM proportionally removes additional current.


The second mechanism that I found is the SYS_CLKIN pin.  On the BF707-EZKIT, it is driven by an oscillator which is not turned off in Deep Sleep.


By removing a zero ohm resistor and adding a testpoint, I was able to manually disable U36 during Deep Sleep.  Doing so, I saw an additional current reduction of as much as 0.140mA on VCORE.  (I also tried this same type of modification with the USB0_CLKIN oscillator (U35) and saw no discernable change.)


There is one typical value cited in the datasheet and "ADSP-BF70x Guide to Power Estimation" cites maximum values over temperature.  (Perhaps the "Clocks disabled" in the datasheet refers to the second mechanism.)


Are these power reduction mechanisms known to Analog, and if so, have they characterized them?