I am working with the AD9361 hdl_2015_r2 example project for fmcomms2. I am trying to pass the digital data from the AD9361 IP to my custom logic which is a simple LUT FIFO (see the enclosed picture and verilog code).
When I use the default loopback function ad9361_bist_loopback(....||.....,2) the transmission is perfect. What I send in the Rx port comes out the Tx port(I use an RF generator and a spectrum analyzer to test it).
Problems emerge when I call the ad9361_bist_loopback(....||.....,0) instead. This time the raw I/Q data is sent to my custom FIFO IP but some where gets corrupted.
My IP works like this: (ADI Reference Designs HDL User Guide [Analog Devices Wiki] ).
As far as I understand the AD9361 IP sets high the ADC and DAC valid signals each time it sends or deamands new data.
I use the rising edges of these signals to store/load data into/from my IP.
I use the #define DAC_DMA macro in my code as well to enable the data transfer (which works well when I don't change the HW and let the Tx branch to transmit a predefined sine through DMA).
When I observe the RF Outputs I see basically noise, that contains some periodic components around the carrier frequency. The spectrum follows the filters band pass characteristics. The signal is strongly stochastical insted of my generator's sine wave.
I suppose that data bits are some how miss aligned or the data rates of the Tx Rx lines are mismatched or some not well documented setup steps are mising from the SDK init code..
If you have any idea what might happen to the data or where I misinterpret the data bus protocol please help me. (I don't have chip scope license for my Vivado, but did simulations on my IP and it worked just like it should.)sincerely