I am working on design for which I need to configure sampling rate at the output of Rx path to 8 Msps and sampling rate at input of Tx path to 16Msps. By reading documentation provided on AD9361 high performance, highly integrated RF Agile Transceiver™ Linux device driver [Analog Devices Wiki] , seems that configuration of sampling rates for Tx path and Rx path are not independent (out_voltage_sampling_frequency as well as in_voltage_sampling_frequency are not entirely independent, by default the both need to match unless adi,fdd-rx-rate-2tx-enable is set. Then RX rate can be twice the TX rate. Does this mean that I need to configure sampling rate to 16Msps and to implement decimation logic for my receiver chain on FPGA?
Thank you in advance on answer.