We are going to use AD9517-3 with its 2 GHz integrated VCO to generate 400 MHz clock for some ADC circuit. The reference clock for the PLL will come from a low-noise 50 MHz source. What phase detector frequency should be selected to achive lowest jitter? Should it be as high as possible, i.e. 50 MHz (the chip allows up to 100 MHz)?
Thanks in advance.