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AD9361- TCXO vs external PLL operation

Question asked by FreddyS on Jul 29, 2016
Latest reply on Aug 1, 2016 by sripad

Dear supporter

My customer is using the AD9361 and is facing a problem when driving 2 AD9361 devices using the same external LO (Required  it in order to achieve phase matching).

The following are the details:

  1. Our AD9361 devices are connected to 2 clock sources:
    1. 80 MHz TCXO source
    2. HMC833 wideband PLL source
  2. The selection between the source is performed using the external_lo_rx_enable and
    external_lo_tx_enable flags in AD9361 drivers (We use No OS drivers)
  3. When AD9361 is configured to use the 80 MHz clock the frequency setting works well
  4. When the AD9361 is configured to use the HMC833 external PLL the AD9361 frequency
    setting is not performed successfully for some reason
  5. Refer  to the picture below with external PLL signal output at AD9361 entrance. It’s a bit
    disturbed by some kind of modulation (We try to find out the source for this modulation)



Few questions:

  1. Can the signal that is shown on the attached picture be the reason for the
    described problem?
  2. What can be other reasons for the described problem?
  3. To make sure that We configure the AD9361 and external PLL properly please confirm
    the following:
    1. The external PLL configured frequency shall be twice the AD9361 configured frequency (for example if the
      AD9361 desired frequency is 2 GHz then the external PLL shall be tuned to 4 GHz)