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Inquiries about configuration of AD9523 on fmcdaq2-ebz

Question asked by MaBolun on Jul 26, 2016
Latest reply on Feb 19, 2017 by rgetz

These days,I am using Xilinx VC707 evaluation board and fmcdaq2-ebz to test JESD204B IP core.

Required CLK signal for AD9680 and JESD204B RX IP core is formed by AD9523,and I have no refrence clock input into AD9523.So I want AD9523 worked at  holdover state. Only PLL2 is working.

The register 0X22D =0X08 ,indicate ad9523 is in holdover.And 0X22C=0XE2,  PLL2 is locked.

But there are no clock output to AD9680. I think there are no clk output.

Here my register:

0X000   00100100

0X004   00000001

0X234   00000001  //IO_UPDATA

 

 

PLL1 setup

0X011   00000000

0X010   00000001

0X013   00000000

0X012   00000001

0X017   00000000

0X016   00000001

0X019   00000000

0X018   10000000

0X01A   0001 1101

OX01B   00110000

0X01C   00000111

0X01D   00000001

 

 

PLL2 SETUP

0X0F0   01110110

0X0F1   00000110

0X0F2   00000011

0X0F4   00000000 

0X0F3   00000010

0X0F4   00000000

0X0F6   00000000 

0X0F5   00111010

0X0F3   00000010

 

CHANNEL 4

0X19C       01

0X19D       01

0X19E       04

CHANNEL 5

0X19F         01

0X1A0        80

0X1A1        04

CHANNEL         6

0X1A2            01

0X1A3            80

0X1A4            04

CHANNEL       13

0X1B7       01

0X1B8       00

0X1B9       04

 

0X230        02

0X231        03

0X232        00

0X233        00

0X234        01

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