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Question about ADSP-21489 PDAP DMA interrupt

Question asked by bitbad on Jul 26, 2016
Latest reply on Nov 4, 2016 by nixiang

Hi,

I have been puzzled by the ADSP-21489 PDAP DMA interrupt recently. In my application, the IF signal is sampled by ADC and sent to ADSP-21489 with the help of FPGA. FPGA is responsible of preprocessing and generating the timings for data transfer with PDAP. The problem is that the ISR for PDAP DMA transfer complete interrupt runs many times while FPGA sends the data only once. After checking the data received by ADSP21489, the data  in the RAM and the length of data are correct.  Maybe there is somthing wrong with ISR in the project, but I have cleared the conresponding registers according the 'ADSP-214xx SHARC Processor Hardware Reference.pdf'.

 

The main function and ISR are listed below, please help me to find out what leads to the ISR runs multiple times within just one transfer.

Many thanks !!

 

//-------------------------------------------------------------------------------------------------------------------------------------------------------------

int g_RxBuf[2][1024];

int g_Pingpong_flag;

int g_DMAIntCounter;

void main(void)

{

     InitPLL_SDRAM(); // Initialize the PLL and SDRAM controller

 

     InitDAI(); // PDAP connections

                      /* DAI_PIN05..20   -------   (PDAP_DAT) */

                      /* DAI_PIN01 -------   (PDAP_CLK) */

                      /* DAI_PIN03 -------   (PDAP_HOLD) */

                      /* DAI_PIN02 -------   (PDAP_STRB) */

     globeInitial();

     interrupt(SIG_P12,dai_low_isr);

     Enable_PDAP(g_RxBuf[g_Pingpong_flag],1024,1);

 

     while(1)

     {

     }

}

 

//-------------------------------------------------------------------------------------------------------------------------------------------------------------

void dai_low_isr(int sign)

{

     int temp,temp1;

 

     temp  = *pDAI_IRPTL_L;      // clear interrupt flag

     temp1 = *pDAI_IMASK_RE;

 

     if ( temp == IDP_DMA0_INT)     // confirm the source of the interrupt before processing the ISR

     {

           g_DMAIntCounter++;      //counter for the PDAP DMA interrupt

 

           while(*pDAI_STAT0 & IDP_DMA0_STAT);

            g_Pingpong_flag++;

            g_Pingpong_flag = g_Pingpong_flag%2;

            Enable_PDAP(g_RxBuf[g_Pingpong_flag],1024,1);

     }

}

 

//-------------------------------------------------------------------------------------------------------------------------------------------------------------

void Enable_PDAP(int DestAdress,int num,int DestIncrease)

{

     int temp;

 

     // disable the CIDP globally

     *pIDP_CTL0 = 0;

     *pIDP_CTL1 = 0;

 

     // clear the PDAP control register

     *pIDP_PP_CTL = 0;

 

     //clear FIFO

     *pIDP_PP_CTL = IDP_PDAP_RESET;

 

     *pIDP_PP_CTL |= IDP_PDAP_PACKING2;      // IDP_PDAP_PACKING2: 16- to 32-bit (packing by 2) ...

 

     // Enable the PDAP Mask bits for DAI_PIN05..20

     *pIDP_PP_CTL |= IDP_P20_PDAPMASK|

     IDP_P19_PDAPMASK|

     IDP_P18_PDAPMASK|

     IDP_P17_PDAPMASK|

     IDP_P16_PDAPMASK|

     IDP_P15_PDAPMASK|

     IDP_P14_PDAPMASK|

     IDP_P13_PDAPMASK|

     IDP_P12_PDAPMASK|

     IDP_P11_PDAPMASK|

     IDP_P10_PDAPMASK|

     IDP_P09_PDAPMASK|

     IDP_P08_PDAPMASK|

     IDP_P07_PDAPMASK|

     IDP_P06_PDAPMASK|

     IDP_P05_PDAPMASK;

 

     // define the active clock edge for the PDAP

     *pIDP_PP_CTL |= IDP_PDAP_CLKEDGE;

 

     // enable the PDAP

     *pIDP_PP_CTL |= IDP_PDAP_EN;

 

     // configure PDAP DMA parameter registers

     *pIDP_DMA_M0  = DestIncrease;

     *pIDP_DMA_C0 =  num;

     *pIDP_DMA_I0 =  DestAdress;

 

     // Enable the PDAP with DMAs

     *pIDP_CTL1 |= IDP_EN0|IDP_DMA_EN0;

     *pIDP_CTL0 |= IDP_DMA_EN|IDP_EN;

}

//-------------------------------------------------------------------------------------------------------------------------------------------------------------

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