Sorry for asking a dumb question but I was confused by data sheet.
The following picture describe my setup. than whats the clock rate of DATA_CLK?
Is it 61.44 MHz or 30.72 MHz?
The confusion came from data sheet AD361_Register_map which describe:
"when using DDR, both edges of DATA_CLK are used(one edge for I and one edge for Q)"
I can't matching this concept with figure 72 of UG-570.
please help me, thank you