A few basic questions about AD9361/FMCOMMS2:
1) Is the ADC linked directly to the DDR via the ADC_DMAC?
2) If I want to add a FFT IP, how should I interface with the ADC, since the FFT core uses AXI stream?
3) Can the control flow of the FFT completely based in the FPGA/PL? Or do I need the CPU/PS to control the flow?