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Schematic and Signal Problems with AD9467-FMC-250EBZ

Question asked by siliconfrog on Jul 22, 2016
Latest reply on Aug 29, 2016 by siliconfrog

Hello,

 

I am currently working on a project to processing some wide-band analog signals.

 

Two available boards are available for me: Zedboard and AD9467-FMC-250EBZ. I work with the reference design in the release branch of "2014_r2", using the hardware project and the no-os APIs.

 

Yet the following questions bothers me.

 

1. The available documents targets to the evaluation board rather than AD9467-FMC-250EBZ. I have not found documents which describes the schematic details.

     1) What is J102 be used for?

     2) The default clock seems to be generated by AD9517, which conflicts to the document (Page 5, UG-200). How can the other clock paths be used?

     3) What are the Jumper J300 and P300 used for?

 

2. I tried to probe the converted signals out to the the pins which are tied to the PMOD JC and JD in the Zedboard. The document of Zedboard says they are capable of 500+MHz signals. I find that the signals deteriorates severely after the frequency of the signal reaches over 10MHz. How can I probe the 250MHz signals out to the Zedboard PMOD by minimizing the loss of signal integrity?

 

Since the board AD9467-FMC-250EBZ is crucial to our project, I am looking forward to your response.

 

Thanks,

Yao

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