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AD9361 Frequency Setting Using External PLL

Question asked by semion_z on Jul 21, 2016
Latest reply on Jul 28, 2016 by semion_z



We have a HW board that includes 2 AD9361 devices connected to Kintex7 FPGA.

Both AD9361 devices can run either by provided 80 MHz clock or by external PLL that is connected to both of them.

When the AD9361 devices are driven by 80 MHz clock the frequency is set successfully within few seconds.

When AD9361 devices are driven by external PLL there is about 2 minutes of delay between the sent command to configure the AD9361 devices and the response/next command execution. The received status from frequency setting is that the frequency is set.

The PLL output frequency is as defined (checked using test equipment).

The AD9361 output was not checked yet using spectrum analyzer.

What can be the reason for this 2 minutes delay?