I read datasheet of AD7091R-5. (Rev. 0)
I felt a doubt about timing of a RESET pin.
Shouldn't it be corrected as figure 35 was drawn by a red line?
Give my best regards.
Reset is a pulse triggered event. Upon power up, the reset signal should be brought high, then the reset pulse negative going edge and also be at a low level (at least 10nS width)should be issued and must return high. The reset line in the timing diagram should look exactly like VDD and VDRIVE except that there is a low pulse some time later.
The answer is really somewhere in between. Upon power up, it may be best to have reset low, but the device really doesn't care about the state of reset at power on. What is most important is that the device see a reset pulse once the supplies are established. The reset event is pulse / edge triggered, not level triggered. This is why a reset pulse is required instead of just holding reset low during power on.
Thank you very much for your answer.
I think I understood about a reset pulse.
But I still doubt about figure 35.
When VDRIVE is 0V, shouldn't RESET be also 0V?
It's a very trivial problem, but I think an important problem.
Thank you very much.I understand that this figure was drawn for a reset pulse, too.Thank you very much again.
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