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AD9361 No-OS signal loopback problem

Question asked by KolosKoblasz on Jul 21, 2016
Latest reply on Jul 26, 2016 by DragosB

Good morning everyone!


Question 1:

I am working with the Zedboard example of the fmcomms2 evalboard. I use the No-OS version.
My first objective is to measure the transmission properties of the 2Tx2Rx configuration. I would like to pass the Rx baseband I/Q data to the corresponding Tx channel.
As far as I know the example project transfers the raw data (via DMA) to the Zedboard's external DDR3 RAM and reads it back to transmit it. (Correct me if I am wrong)


Instead of the aforementioned procedure, the AD9361 after configuration starts producing a high power (roughly -8dBm) sine on the Tx ports, completely neglecting the received signal. The frequency of the sine wave is exactly 1MHz greater than the TxLO signal.


Creating this loopback functionality is vital for my aplication because I will modify the row basband data with dedicated custom IPs.


In dac_core.c (during the successful initialization procedure) the folowing function call causes the unwanted sine's appearance :



void dac_init(struct ad9361_rf_phy *phy, uint8_t data_sel, uint8_t config_dma)





dac_write(phy, DAC_REG_CNTRL_2, reg_ctrl_2);

  dac_read(phy, DAC_REG_VERSION, &dds_st[phy->id_no].pcore_version);


  switch (data_sel) {

  case DATA_SEL_DDS:

  dds_default_setup(phy, DDS_CHAN_TX1_I_F1, 90000, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX1_I_F2, 90000, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX1_Q_F1, 0, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX1_Q_F2, 0, 1000000, 250000);



  dds_default_setup(phy, DDS_CHAN_TX2_I_F1, 90000, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX2_I_F2, 90000, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX2_Q_F1, 0, 1000000, 250000);

  dds_default_setup(phy, DDS_CHAN_TX2_Q_F2, 0, 1000000, 250000);




  case DATA_SEL_DMA:




Question 2:

I tried to bypass the DMA chain by connecting the 64 bit data output of the  utila_d9361_adc_pack to the input of the utila_d9361_dac_upack. The IC preserved it's behaviour regardless of my modifications.

At which point should the signal chain be interrupted to implement unique DSP functions?




I am looking for your helpful answers.
Thank You!


Kolos Koblasz