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PLL Lock issue - AD9910

Question asked by amitkumar on Aug 4, 2011
Latest reply on Aug 5, 2011 by KennyG

I've two questions regarding the usage of onboard or external clock source for AD 9910


I've been able to achieve the PLL lock at 500MHz using 25MHz on board crystal. Our main requirement is to lock the PLL at 640 MHz. The components (cap & res) selected for the same are as per the calculation indicated in the PLL_Loop_Filter_Tool.xls (sheet attached).



1. To achieve a lock at 640MHz we have replaced the on board 25 MHz crystal with a 20 MHz crystal. The values of capacitors and resistors to achieve PLL lock have been calculated and the same have been mounted on board (ref attached xls), but the PLL LOCK is not stable (keeps going ON and OFF).


My first question is -  Is it really necessary to have a fix 25MHz crystal on board?


2. We have tried giving external clock of 20MHz (sine wave) from a signal generator and locking it at 640 MHz but LOCK was not stable.


Please help me on this!

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