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HMC720LP3E @ 10-20Mhz

Question asked by massronchi on Jul 20, 2016
Latest reply on Aug 15, 2016 by salemdar

Hi All,

I want use a HMC720LP3E as fanout buffer with a very low skew between the two output ports, the input clock will be 10-20 Mhz and I need to interface two LMK04828 (http://www.ti.com/lit/ds/symlink/lmk04828.pdf) that accepts a LVDS or LVPECL standard (see pag 96). The two LMKs are at 20cm away from the source after an high speed connector, considering the cost of this chip i need to understand which skew i will obtain on the input after the AC capacitor and Rt for proper termination. The LMK has a internal bias so i think that the right termination is the following could someone verify if is it correct? The input must interface a lvpecl output of the  NB7L572 (http://www.onsemi.com/pub_link/Collateral/NB7L572-D.PDF) .

 

Thanks

Maxx

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