We used AD9279 for a long time, to correctly read the data bits on LVDS interface of AD9279, we had developed an algorithm on FPGA(using Xilinx Kintex-7) as below :
1. use the IDELAY primitive to align the phase of DCO/DOUT to 90 degree
2. use the bitslip operation to reconstruct correct bit set of each sample
Main concept were derived from XAPP524(http://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf ) of Xilinx, with some modification to fit our requirement.This algorithm works just well with AD9279, from 20MHz sample rate to 80MHz.
Recently, we had made a few new boards, some were populated with AD9279, and the others with AD9670. But we found data on LVDS interface cannot be correctly read on the AD9670 boards, for example, if we set AD9279/AD9670 to test mode and choose "Checkerboard" pattern, the AD9279 boards successfully read the pattern as "1010,1010,1010,1010" or "0101,0101,0101,0101", but in AD9670 boards, data read could be "0010,1010,1010,1010" (MSB is wrong) or "1010,1000,1010,1010"(bit 10 is wrong). This problem only happen on AD9670 boards.
I had tried to set LVDS related register settings(ex. 0x15 : LVDS drive strength, 0x16 : DCO clock delay, phase adjust) but didn't help.
I had struggled on this problem for a long time, looking forward to helpful suggestions.