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Facing problem with ADDI7100 AFE

Question asked by mohan.pugos on Jul 20, 2016
Latest reply on Jul 31, 2016 by TFAnalog

In our new CCD borad, we have used 6 ADDI7100 AFE chips. We have generated timing signals from FPGA and also the 3-wire serial interface from the same. We have verified the CCD signal input and also written the startup command (0x3 to 0x5 register, please see attachment). But we get only a constant value as digital output, always. Specifically, only the D10 pin is high; every other data pin is low.

I assume all other registers except 0x05 can be left in their default state. The data clock frequency is 30 MHz, same as SHD and SHP generated according to timing diagrams. PBLK tied to high. CLPOB pulsed low for 20 cycles be readout period.

It seems the AFE is not starting up at all or is stuck in some unknown state. Please help.

One observation to note is that, while the startup command is being written into the 3-wire serial interface, the data outputs are switching. But no reaction after that.

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