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AD9914 Sync Clk Issue

Question asked by Karthik_FAE on Jul 18, 2016
Latest reply on Jul 18, 2016 by LouijieC

I have an issue with Sync Clk. Im using 1860 input reference and trying to get clean 650 MHz to 800 MHz output.

But this Sync Clk which is a divide by out of input reference is appearing at the Fout. We tried lowing the Sync_Clk Pin in CFR2 but still no effect on the output. This peak is appearing at 77.5 MHz at 45 dBc level where I m trying for 60 dBc. How does Bit 11 from CFR2 will help. 

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