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ADV212 Encode frame loss and sync

Question asked by tentenberk on Jul 15, 2016
Latest reply on Jul 18, 2016 by tentenberk

Hello All,

 

We are using ADV212 as a JPEG2000 encoder for a PAL video captured by ADV7180 which is connected to ADV212 via Video bus of ADV212. The host interface is connected to an FPGA so that we can capture the compressed image. The register settings for both of the devices will be given below.

 

We are using the embedded time codes for the frame synchronization therefore we did not tie the HSYNC,FIELD,VSYNC signals on both of the ICs. I have managed to load the firmware correctly so that ADV212 is in DCS DMA mode and captured compressed images that are de-interlaced by the ADV212 by using the VFORMAT = 9.

 

The configuration sequence starts by configuring the ADV7180 and when it is "in lock", the configuration of ADV212 starts. We have applied this sequence so that we would not be missing any frames from ADV212.

 

However, the problems we see in output of the ADV212 is

- Some frames can be dropped and not outputted from ADV212, this is examined by having the ADI header option on and checking compressed image index field in the header. Sometimes the image index field does not increment as we have expected, there can be losses, like previous index can be 8 but the next index can be 10 instead of 9. What can be the issue for this?

 

-Second problem is although we are streaming a still image to the ADV7180 with a pattern generator adjusted for PAL video, the compressed images sometimes can be outputted as out of sync. The images will be given below also. We are stuck at this point and feel that we have tried everything we can according to the datasheet(s) of ADV212 and ADV7180.

 

Is there any indicator in the ADV212 that the ADV212 is locked to the video input. I guess the ADV212 is starts to output compressed image data without waiting to lock to the video.

 

We really like to hear from you soon as soon as possible.

 

Thanks in advance

Berk

 

ADV212 Configuration Sequence

     Register Address & Register Data

     X"E" & X"0008",

      X"F" & X"0004",

      X"D" & X"008A",

      X"8" & X"0005",

      X"9" & X"0005",

      X"A" & X"0005",

      X"B" & X"0000",

   

      X"D" & X"008D",

      X"8" & X"0005",

      X"9" & X"0005",

      X"A" & X"0005",

      X"B" & X"7F00",

      -- ADV 212 Programming Guide Encoder Parameters Page 43 --

      X"C" & X"0900",

      X"C" & X"0503",

      X"C" & X"0300",

      X"C" & X"0000",

      X"C" & X"0100",

      X"C" & X"61A8",

       X"C" & X"000B",

       X"C" & X"00F1",

 

       X"A" & X"FFFF",

       X"B" & X"1408",

       X"C" & X"0002", -- EDMOD Register VALUE --

       X"5" & X"0402",

       X"6" & X"0000",

       X"A" & X"FFFF",

       X"B" & X"141C",

       X"C" & X"0002", 

       X"A" & X"FFFF",

       X"B" & X"1408",

       X"C" & X"0003",

       X"7" & X"0000",

       X"6" & X"FFFF",

       X"A" & X"FFFF",

       X"B" & X"044C",

       X"C" & X"0000"

 

 

ADV7180 Configuration Sequence

 

Register Address & Register Data

     X"00" & X"06",

     X"03" & X"0C",

     X"0C" & X"34",

     X"14" & X"30",

     X"04" & X"D7",

     X"31" & X"02",

     X"3D" & X"A2",

     X"3E" & X"6A",

     X"3F" & X"A0",

     X"58" & X"04",

     X"0E" & X"80",

     X"55" & X"81",

     X"0E" & X"00"

 

The attached images are as follows:

test-1.j2c first frame capture from the ADV212 and it is out of sync. Frame is vertically shifted.

test-8.j2c is the 8th frame captured from ADV212 and it is out of sync. Frame is vertically shifted.

9th image is not outputted from ADV212.

10th image seems to be the image capture when ADV212 is trying to get into lock.

11th image is the vertically locked true image.

 

After 11th captured image, all the captured images seems to be in vertically in sync or lock.

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