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ADV7511 on zc706 can not display

Question asked by pxinz01 on Jul 14, 2016
Latest reply on Jul 19, 2016 by JeyasudhaMuthuPerumal

FPGA Reference DesignsRCharyJohokaushalstevebDavidMJohannesH
HI!

I‘m  initialing the adv7511 on the zc706 board via the FPGA-VHDL project,but i can not get the signal on the screen. i have done  some changes from the previous project which it works well on the zedboard.

can someone give me some suggestions  that  i can fellow to check up the code ?AND  what might be the reason that there is no signal on the screen,thanks a lot!

 

here is the register set:

when x"00" => reg_value  <= x"4100"; -- Powerup please

            when x"01" => reg_value  <= x"9803"; -- Must be set to this

            when x"02" => reg_value  <= x"9AE0"; -- Must be set to this

            when x"03" => reg_value  <= x"9C30"; -- Must be set to this

            when x"04" => reg_value  <= x"9D61"; -- Must be set to this

            when x"05" => reg_value  <= x"A2A4"; -- Must be set to this

            when x"06" => reg_value  <= x"A3A4"; -- Must be set to this

            when x"07" => reg_value  <= x"E0D0"; -- Must be set to this

            when x"08" => reg_value  <= x"5512"; -- Must be set to this

            when x"09" => reg_value  <= x"F900"; -- Must be set to this

            when x"0a" => reg_value  <= x"9d01"; -- pixel divider

            when x"0b" => reg_value  <= x"1506"; -- YCbCr 422, DDR, External sync

            when x"0c" => reg_value  <= x"4810"; -- Right aligned data (D23 downto 8)

            when x"0d" => reg_value  <= x"1636"; -- 8 bit style 2, 1st half on rising edge - RGB output

            when x"0e" => reg_value  <= x"1700"; -- output aspect ratio 16:9, external DE

            when x"0f" => reg_value  <= x"1800"; -- CSC off

            when x"10" => reg_value  <= x"AF00"; -- DVI mode

            when x"11" => reg_value  <= x"4c04"; -- Deep colour (HDMI only?)

            when x"12" => reg_value  <= x"4000"; -- Turn off additional data packets

            when others => reg_value <= x"ffff";

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