AnsweredAssumed Answered

Queries about ADRF6755's LO Leakage

Question asked by WayneQ on Jul 14, 2016
Latest reply on Nov 8, 2016 by LKelly

Hi, there

We have used  ADRF6755 in a direct RF UHF DVB-T modulator with AD9783 az IQ signal generator which is DC coupled to ADRF6755 input and AD9783's AUX DAC are used to remove LO leakage at ADRF6755 output.

AD9783 is used to generate output spectrum at IF freq. 30MHz so LO and image components exist in the UHF band at 30MHz and 60MHz distance from output spectrum, therefor, we should calibrate for DAC values(I-offset,Q_offset,I_gain,Q_gain plus a phase component implemented on FPGA connected to AD9783) to remove LO and image components.

But there is a problem, after offset calibration and removing LO leakage, every time I turn ON and OFF the system, LO leakage changes and I should set new offset values for the same frequency setting on AUX DACs to remove LO at ADRF6755 output.

I also observe that if I change the frequency to a new value and then again set the previous frequency (which AUX DAC values are set to remove the LO leakage) again LO leakage value changes.

As an example if I set the the freq at 530MHz (single tone) and remove the LO to -68dBc by AUX DAC and then change the freq to 860MHz and again set the freq to 530MHz without changing AUX DAC values now I have -49dBc LO leakage at ADRF6755 output (this is not occur every time but most of the times occur after four to five times changing the freq) and the important observation is that LO leakage always switches between only 2 values in this example -68dBc and -49dBc. It seems that synthesizer has 2 states when it locks(from the view of LO leakage) i.e., with constant AUX DAC values, in one state after lock LO leakage is -68dBc and in another state LO leakage is -49dBc

Please guide us through this issue, this is very critical for our devices because output spur in UHF band should always set under -60dBc  and since we have set a calibration table in our device to remove LO at every output frequency we expect to have spur free output spectrum in every frequency at every time (I have ignored compensations for temperature change on calibration table in this discussion)

Consider that LO leakage switching between these values occur only when I reprogram the same frequency in ADRF6755. After every programming  LO leakage is constant until I reprogram the ADRF6755.

It switches only between 2 values and not depend to time and temperature. After every reprogramming of ADRF6755 the LO leakage randomly switches between these 2 values and this happens immediately after programming is done, so I result from this performance that LO leakage change problem is not dependent to time and temperature.
As I explained above we see this performance just by reprogramming the ADRF6755 and the LO leakage change occurs immediately after programming is done, so I think this problem refers to ADRF6755 itself. since we are testing in single tone the digital values from FPGA are constant and we have not changed any parameter (such as AUX DAC values) in the DAC. At all tests we have just reprogrammed the ADRF6755 and have seen this performance.
For your confidence, we have also measured the DC values at ADRF6755 inputs, they do not change while LO leakage is changing at every programming.
I have again attached our ADRF6755 programming source code here. 

Initialization values for CR0 to CR30:

static uint8_t DefaultRegVal[] = {
0, 0x00,
1, 0x00,
2, 0x00,
3, 0x04,
4, 0x01,
5, 0x00,
6, 0x00,
7, 0x00,
8, 0x00,
9, 0x30,
10, 0x01,
11, 0x00,
12, 0x18,
13, 0xE8,
14, 0x00,
15, 0x00,
16, 0x00,
17, 0x00,
18, 0x60,
19, 0x80,
20, 0x00,
21, 0x00,
22, 0x80,
23, 0x70,
24, 0x18,
25, 0x19,
26, 0x00,
27, 0x07,
28, 0x09,
29, 0x80,
30, 0x03

ADRF6755 programming function:

ERROR_T ADRF6755::SetFrequency(uint32_t x_Val)
int i;
uint32_t FLo, nInt, nFrac;
uint8_t RFDiv, CR27_4, val;
float N;

FLo = x_Val;

CR27_4 = 0;
if ((FLo > 100000000ul) && (FLo <= 144375000ul))
RFDiv = 4;
else if ((FLo > 144375000ul) && (FLo <= 288750000ul))
RFDiv = 3;
else if ((FLo > 288750000ul) && (FLo <= 577500000ul))
RFDiv = 2;
else if ((FLo > 577500000ul) && (FLo <= 1155000000ul))
RFDiv = 1;
else {
CR27_4 = 1;
RFDiv = 0;

N = (pow(2, RFDiv) * FLo) / 10000000ul;
nInt = floorf(N);
nFrac = (N - nInt) * 0x2000000; // 0x2000000 = 2^25

val = GetValInTable(27) & (uint8_t)(~M_BIT(4));
val |= (CR27_4 << 4);
SetValInTable(27, val);

val = GetValInTable(28) & 0xF8;
val |= (RFDiv & 0x07);
SetValInTable(28, val);

val = GetValInTable(7) & 0xF0;
val |= ((uint8_t)(nInt >> 8) & 0x0F);
SetValInTable(7, val);
SetValInTable(6, (uint8_t)(nInt));

SetValInTable(0, (uint8_t)(nFrac));
SetValInTable(1, (uint8_t)(nFrac >> 16));
SetValInTable(2, (uint8_t)(nFrac >> 24));

for (i = (sizeof(DefaultRegVal) / 2) - 1; i >= 0; i--) {
Write_Reg(DefaultRegVal[i*2], DefaultRegVal[(i*2) + 1]);

return 0;


Could you please help with the issue or give some comments on it?


Thanks so much for your kindly help and support!