I'm writing software to have a BF537 processor talk to a Mindspeed M21125 via the SPI interface. I've run into a couple of issues:
- The M21125 requires 18 bits of data: 2 special bits, 8 address bits, and 8 data bits. To keep things as simple as possible, I'm trying to perform two back-to-back transactions without using DMA or interrupts. I've setup the SPI to use 16 bits per transaction so 2 SPI transactions are needed per data transfer. I'm working only with read operations at the moment. The problem is that the 537 brings the SSEL line high between the two transactions. Unfortunately, the M21125 resets its interface circuitry for a new operation when it sees the SSEL falling edge.
- The second problem I've run into is that on a write operation, the M21125 needs an additional SPI clock cycle after SSEL goes inactive to clock the data from the shift register into the destination register. I cannot find how to cause the 537 to continue its clocking beyond the SSEL.
I was thinking that DMA might solve the first issue but I'd rather not bring it into the picture for just two transactions.
I have no idea how to deal with the 2nd issue.
Any help would be greatly appreciated.