Hello, I'm studying transceiver system on Zedboard connect with fmcomms2 module, I transmitted and received signal when config and run available C file of your Company. But When I see design of system on FPGA, I dont understand rule of communication between DAC unpack IP and AD9361.
- the first question,Output of DAC unpack to AD9361 only have dac_data[15:0] and input of util_dac_unpack IP from AD9361 is dac_enable and dac_valid. Why can AD9361 know when dac unpack ip doesnt have data, or dac unpack ip is busy?
- the second question,when are dac_valid and dac_enable from AD9361 to util_dac_unpack IP low(0) and high(1)
- I see AD9361 DMA have a signal (which is fifo_underflow connect to AD9361),what is purpose of this signal?
Thank you very much!