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Question asked by theaman24 on Aug 2, 2011
Latest reply on Aug 4, 2011 by Andreas



I'm using a BF538F EZ KIT and am trying to figure out sclk and cclk.  The EZ KIT supplies the blackfin processor with an input clock (maybe I can find this value in the BF538F EZ-KIT Lite Hardware Reference Manual?).  And I should use the PLL registers (PLL_DIV, PLL_CTL, PLL_STAT, PLL_LOCKCNT) to set sclk and cclk from this clkin? 


The Hardware Reference Manual shows a table of how sclk can be divided down from VCO, shown in the screenshot below.


Is this VCO the same as CLKIN from the EZ KIT? Or where does VCO come from?

If they are different, does VCO or does CLKIN get divided down to SCLK?

And where can i find out what these values (VCO and CLKIN) are so I can correctly set SCLK?


Thanks for the help!