I'd like to ask some questions regarding the Min value of the ADuC7060's External Reference Input Range of 0.1V (on page 7 of the datasheet) for PGA=4 to 64. I suppose the reason for this limit is similar as in case of the differential ADC inputs, where a lower limit of 100mV applies if PGA gain is ≥ 4. It suggests the presence of a buffer.
Does this limit of 0.1V also apply to the "(AVDD, AGND) divide-by-two" setting of ADC0REF, in case the PGA setting is ≥ 4, and ADC1REF? (I would suppose, yes.)
I've seen some example circuits, e.g. in AN-0970: RTD Interfacing, p.3, on page 56 of the datasheet, and in the schematics of the ADuC706x's evaluation boards, where VREF- is directly connected to AGND. This suggests that the PGA gain must be < 4 in these examples. Though, in the example source code for RTD measurement, both IAR/ADC0_RTD/main.c and RTD_PieceWise_Linearization/RTDLinearMain.c, a gain of 32 is used. Shouldn't this be <4, given that VREF- is at 0V?
In contrast to the lines above, DOC-15395 states that there are no buffers on VREF+ and VREF-, hence no 0.1V limits applying.
In case I'm not misunderstanding the meaning of the Min value, it would be nice if you could clarify whether the Min value in the data sheet is correct, and, in case it is, why often VREF- is tied to AGND, even if the PGA is used.