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Question asked by fhartery on Aug 2, 2011
Latest reply on Aug 9, 2011 by DSB

I am intending to use the AD9910 as a linear FM, highly phase stable, retriggerable DDS aligned to an external system clock of 100 MHz. I am sort of concerned that the internally generated 1 GHz PLL design will possibly create sweep to sweep jitter.


What I am not referring to is therefore not a phase/frequency programming alignment of the internal programming registers. What I am referring to direct access to the 1 GHz PLL to create the start/stop of a sweep timing. Is this subject to an application note. If not what are the draw backs and workarounds here. Thanks!