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AD9288 Digital Input Voltage Tolerance

Question asked by gda on Jul 12, 2016
Latest reply on Jul 18, 2016 by gda

Hello, I'm confused about the AD9288 datasheet specification for the voltage tolerance of the digital inputs.  Sheet 3 of the datasheet gives a minimum value for LOGIC-1 (2.0v).  However, the datasheet does not specify the maximum value for LOGIC-1.  Sheet 7 of the datasheet provides the absolute maximum specifications for the device (VDD + 0.5V). However, operating at the absolute maximum level is not recommended.


My plan is to tie VD and VDD of AD9288  to a 3.0V nominal supply.  However, the ENCA, ENCB inputs will be driven by a LVCMOS clock driver that is powered by 3.3v.  Therefore, the VOH of the clock driver will be 0.3v higher than VDD of the AD9288.  Is this a safe interfacing scheme?  If not what do you think about the following alternatives?


Alternative 1: Operate clock driver from a 3.0V power supply -- the same as AD9288 VDD supply.

Alternative 2: Operate clock driver at 3.3V    Operate AD9288 VDD = 3.3V      AD9288 VD = 3.0v