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Xilinx support for run time dynamic sample rate changing

Question asked by stevereine Employee on Jul 12, 2016
Latest reply on Jul 15, 2016 by gverma

I've got a customer who would like to be able to dynamically change their sample rate at run time. They are using a Xilinx FPGA solution. Without reloading the FPGA .bit file when the sample rate is changed, they want to be able to just bring the JESD link down, reconfigure the various internal PLLs associated with the JESD link to the new sample rate, then bring the JESD link back up.

 

thanks!

 

Steve

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