I have a RF front end board using DAC AD9122 and ADC AD9434. I started my FPGA design from the FMCOMMS1 reference design (hdl-hdl_2015_r2 with no-OS). Everything works well except that of course the receive signal is mixed due to the use of a different ADC (AD9434 single 12bit channel instead of AD9643 dual 14bit channel).
So I replaced axi_ad9643_v1_0 / util_wfifo_v1_0 / util_cpack_v1_0 of the FMCOMMS1 reference design by axi_ad9434_v1_0 directly connected to the axi_dmac_v1_0.
What should I do with the delay_clk port of the axi_ad9434? The only reference I have is ADI Reference Designs HDL User Guide [Analog Devices Wiki] and the pin is not described except for the DAC.
I connected the delay_clk pin to the MIG ui_clk and I got this error while running the design implementation:
i_system_wrapper/system_i/axi_ad9434_0/inst/i_if/i_serdes_clk/i_mmcm_drp/i_mmcm: The MMCME2_ADV with CLKINSEL tied low requires the CLKIN2 pin to be active.
It seems to be an internal signal and I tried to compile the AD_9434_FMC_ZC706 project and got no error.
Do you have any idea of the problem?
Thanks for your help.