Is there a deterministic clock skew between the CLKIN input and the SCLK0/SCLK1 outputs on the BF561? I'd like to use the ARDY signal in the AMI interface but I don't have access to these output clocks in my FPGA, so I was hoping to duplicate the SCLK generation in a PLL inside my FPGA. The CLKIN input is driven by an FPGA output, so I have access to the source clock from which SCLK is derived. I should be able to duplicate the steps to get from CLKIN to SCLK, but in order to constrain the timing on ARDY, I need to know what (if any) clock skew there is internal to the BF561. Also, I need to know that this skew is constant and deterministic, i.e. it won't change from one power-up to the next.