I'd like to use an AD9913 DDS in a phase sensitive application where the typical set-up is REF_CLK input is 49.805 MHz, and the DAC O/P is 49.8025 MHz. The PLL multiplier is set to 5. When first activated, there will will be some specific latency between the REF_CLK I/P and the DAC O/P. If the REF_CLK I/P is interrupted for several seconds, when the signal is restored (no frequency changes) is there a process by which I can ensure that the latency is the same as originally measured? I'm assuming that this is not the same as the Data Latency figures?