Hi,

I can't see my possible error so I'm asking it here.

I've used the 256pointFFT example on the ADSP-21469 EZ-Board.

Running on 450MHz the calcuation time is around 21µs (measured with GPIO changing before and after the accelerator DMA operations).

But according to the ADSP-214xx_hwr_rev1.1.pdf the time should be:

2*256*2 + 256*log2(256) + 2*256 = 3584 cclk which is around 8µs.

Where is my error?

Regards

Christian

Hi all,

in the meantime I've got an answer.

The formula is for PCLK cycles and for each input DMA (coef and data) are 2Nx2 PCLK cycles necessary.

So in total:

(2*256*2 + 2*256*2 + 256*log2(256) + 2*256*1) * 2 = 9216 CCLK cycles i.e. 20.48µs @450MHz.

(coef + input data + FFT + output data)

Regards

Christian