AnsweredAssumed Answered

ADV7180 - Losing Vertical Sync

Question asked by muzza on Aug 2, 2011
Latest reply on Aug 3, 2011 by DaveD

I am using a Xilinx video daughter board with an ADV7180 and streaming the ITU-R 656 stream into a FPGA.

 

Unfortunately, I am getting no vertical lock when I inject the ADV7180 with a PAL-B composite signal applied to AIN3.

 

I have tried autodetect, and manually setting the video selection to PAL/B/G etc, with no difference. I have also left register 0x00 at it's default (unwritten)and applied the signal into AIN1 with no effect.

 

If I read Status register 1 (0x10), it indicates that it has detected PAL B/G/H/I/D.

 

Below are the settings I am using in `C' code that I am using:-

 

 

{0x00, 0x04}, 

{0x04, 0x54},

{0x17, 0x41},

{0x31, 0x1A},

{0x3D, 0xA2},

{0x3E, 0x6A},

{0x3F, 0xA0},

{0x55, 0x81},

{0x0E, 0x00},

{0x58, 0x01},

{0x37, 0x00}

 

An example of what I am getting out of the ADV7180 is attached.

 

Any ideas ?

 

 

Cheers

 

Muzza

 

 

 

 

 

 

 

 

 

 

 

 

 

Attachments

Outcomes