Here is the problem (testing is still ongoing): Our firmware team reported getting occasional timeouts waiting for the /RDY bit in the status register. Timeouts are rare which is why its time consuming to test - about 1 per 8+ hours of 1 sample/second operation. Firmware manually change channels (no sequencing), with buffer and chop enabled - each of 8 channels, followed by temperature channel, is individually sampled, waited until status reg bit ready and then read. The firmware guys observe that everytime they get a ready bit timeout, the ERR bit is also set in the status register. This does not seem to be data channel related because the Temperature channel presents the same problem. This happens on multiple boards, for multiple input data values, and the temperature channel. So the ERR does not seem to be caused by data range.
To be confirmed (still testing):
(a) is /RDY bit is prevented from going low when ERR = 1?
(b) what is status of NOREF bit when ERR = 1?
Are there any other things that we should be trying in order to debug this timeout issue?