Where you can find the timing diagram with the AD9248 or similar chips, thank you very grateful!
In addition to the order of the pin for software settings and data output format, please provide a reference, thank you!
Pin out w/ description and timing diagram are shown in the datasheet. The Ad9248 does not include SPI port for internal device configuration thus no software settings required.
The timing diagram in figure 2 of the datasheet shows the data transition region (where data is invalid) relative to rising edge of CLK as being anywhere between 2 to 6 nsec (worse case) after rising edge of CLK. This suggests that the host "latch" would need to have min hold time of 2 nsec and set-up time that is 1/FCLK-6 nsec.
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